FIG. 1 illustrates the typical layout of a known computer system, in which a processor 1 and one or more bus masters 2 (e.g. I/O device controllers) are coupled to a memory system 4 via a bus 3.
The memory system 4 comprises a memory controller 5 and a memory module 6 having a plurality of memory banks 7. Access to the memory module 6 is shared by the processor 1 and bus masters 2 and is controlled by the memory controller 4. The memory controller 4 executes access requests received from the processor 1 and bus masters 2 over the bus 3, e.g. read data from or write data to the memory module 6. The memory module 6 stores both program data (i.e. instructions to be executed by the processor 1) and non-program data.
In one particular configuration, shared access is provided to a memory bank 7a storing both program data and non-program data. Whilst storing both program and non-program data in a single memory bank makes efficient use of the available memory, the configuration has the disadvantage that requests to read program data by the processor 1 are delayed if the bank 7a is already being accessed by a bus master 2.
When data stored in a dynamic random access memory (DRAM) bank is accessed, the row of memory cells storing the data is activated (or opened) for access. The row of cells remains activated until such time as a precharge signal is received, whereupon the row of cells is deactivated (or closed). Alternative data stored in an alternative row of cells cannot be accessed until such time as the previous row of cells has been deactivated. There is therefore a delay before data can be read from a memory bank that has already been accessed. Moreover, there may be latency between successive access requests, i.e. the time between two successive access requests (i.e. the cycle time) may be greater than the time taken to complete an access request (i.e. the access time).
Accordingly, when access to a memory bank 7a storing program data is shared, the processor 1 is not able to gain immediate access to the program data if the memory bank 7a is already being accessed by a bus master 2. Consequently, in configurations for which shared access is permitted to a memory bank 7a storing program data, there is an increased latency in reading program data.
The latency of requests to read program data is ideally as short as possible such that the processor 1 is able to quickly retrieve and execute processor instructions. Accordingly, in an alternative configuration, a single dedicated memory bank 7b stores only program data, i.e. access to the memory bank 7b is not shared but it restricted to access by the processor only 1. Whilst this provides for shorter access times in reading program data, only a small fraction of the memory bank 7b is typically used and consequently memory usage is inefficient.